APECS - Fraunhofer IAF

As part of the EU Chips Act, the Research Factory for Microelectronics Germany (FMD) is establishing the APECS-PL pilot line (Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems) in collaboration with European partners. The goal is to create an end-to-end platform for the development, integration and pilot-scale manufacturing of modern microelectronic systems, as well as to accelerate the transfer to industrial applications. By providing large industrial companies, SMEs and startups with easier access to cutting-edge technology, the APECS pilot line will lay a solid foundation for resilient and robust European semiconductor supply chains.

Contribution of Fraunhofer IAF

As a partner institute in the FMD, Fraunhofer IAF is developing novel InGaAs-on-Si and GaN-on-SiC chiplets for high-frequency applications, as well as microbump interposers, within the framework of APECS. Due to their outstanding performance in key parameters such as noise, output power, and efficiency, these technologies are particularly well-suited for high-frequency applications and promise innovations in measurement technology, communications, radar technology and sensor technology.

In addition, Fraunhofer IAF is driving the targeted expansion of its infrastructure and the transition of manufacturing to wafer sizes established in the industry. These measures ensure long-term compatibility with industrial standards and facilitate the transfer of new technologies into scalable, marketable solutions.

Significant progress since the project began

Comparison of a 4-inch wafer and a 6-inch wafer — © Fraunhofer IAF
The institute is expanding its production capacity to include 6-inch wafers in order to facilitate the transition to industrial-scale production and improve manufacturing quality.

Since the start of the project, Fraunhofer IAF has focused in particular on establishing a technologically leading and future-proof infrastructure. In parallel, significant progress has been made in the development of key technologies for chiplet-based system integration. These include, in particular, the implementation of reliable interconnection technologies using electroplated indium bumps, which enable efficient electrical connectivity and improved heat dissipation, as well as the development of low-loss interposer structures. In the field of quartz interposers, initial successful approaches to the fabrication of high-precision substrate through-silicon vias using laser-based and wet-chemical etching processes were demonstrated, which form the basis for high-frequency applications.

Building on these technological developments, the implementation of initial demonstrators was initiated in collaboration with other Fraunhofer Institutes to validate the performance of the developed approaches in a system-oriented manner.

One demonstrator aims to achieve the heterointegration of the high-frequency GaN chiplet with the Si chiplet into a single system. This utilizes Fan-Out Wafer-Level Packaging (FOWLP) technology, which enables low-loss and scalable heterointegration up to the highest frequencies. This results in a complete system that combines the high power density of GaN technology with the integration density of CMOS. This creates a novel system approach that forms the basis for future applications in high-frequency technology, sensor technology and communications.

In addition, Fraunhofer IAF is collaborating with the Leibniz Institute for Innovative Microelectronics (IHP) to develop a highly innovative demonstrator for a sub-THz mHEMT-BiCMOS transceiver based on an interposer. The goal is to realize a next-generation ultra-wideband, high-resolution sensor by combining SiGe BiCMOS and mHEMT chiplet technologies in a high-performance heterogeneous integration with excellent RF performance and integration density. The demonstrator represents an important step toward high-performance sub-THz sensor systems for future applications.

PROJECT TITLE

APECS — Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems

DURATION

2024–2029

FUNDING

APECS is co-funded by the Chips Joint Undertaking and national funding authorities of Austria, Belgium, Finland, France, Germany, Greece, Portugal, Spain, through the Chips for Europe Initiative.

COORDINATION

Fraunhofer-Gesellschaft

IMPLEMENTATION

Research Fab Microelectronics Germany (FMD)

OBJECTIVES

Bridging application-oriented research with innovative development in heterogeneous integration, specifically through the use of emerging chiplet technologies.
Delivering robust and trustworthy heterogeneous systems in order to significantly boost the innovation capacity of the European semiconductor industry
Supporting European microelectronics by standardizing integration technologies and unlocking new functionalities within the system-technology co-optimization (STCO) approach
Supporting European companies to develop advanced products with high yields, even in medium quantities, at competitive costs
Providing a wide range of technologies on a single platform to offer large enterprises, SMEs and tech start-ups a one-stop shop that simplifies processes and ensures efficient collaboration at every stage
Contribution a carbon-neutral and circular economy through focus on eco-design and green manufacturing initiatives

Funding sources

Further Information

APECS website

Learn more about the APECS pilot line on the APECS website.

More Info

APECS — Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems

Fraunhofer IAF's APECS publications